1. Field of the Invention
The present invention relates to clock and data recovery systems and, more specifically, to M-level pulse amplitude modulation (M-PAM) receivers.
2. Description of the Related Art
M-level pulse amplitude modulation (M-PAM) is a modulation technique that can be employed to reduce bandwidth requirements in data communication systems. Generally, an M-PAM transmitter modulates a carrier with one of M different amplitude levels per symbol, allowing log2M bits of data to be transmitted per symbol interval. 4-PAM is a subset of M-PAM where a carrier is modulated with one of 4 different amplitude levels per symbol, allowing 2 bits of data to be transmitted per symbol interval. 2-PAM corresponds to the common bi-level or binary modulation scheme.
Data recovery of a transmitted M-PAM signal at a receiver is typically achieved using M−1 data slicers, an edge slicer, a phase detector, and a clock recovery circuit. A slicer compares an input signal with a reference signal and outputs one logic level when the input signal exceeds the reference, and another logic level if the input does not exceed the reference. A slicer is typically implemented with a voltage comparator, an amplifier, and a D-type flip-flop (D-FF). The voltage comparator compares an input signal with a reference voltage and outputs one voltage (typically close to the positive rail or supply voltage of the voltage comparator) when the input signal exceeds the reference, and another voltage (typically close to zero volts in a non-differential implementation or the negative rail or supply voltage in a differential implementation) if the input does not exceed the reference. The output of the voltage comparator is fed to the amplifier, where its amplitude is adjusted to a range appropriate to the D-FF. The output of the amplifier is then sampled by the D-FF. M−1 threshold voltages corresponding to the M−1 data slicers are distributed evenly between the M symbol amplitude levels of the modulated carrier in an interleaved fashion, ideally with each threshold centered between two adjacent symbol amplitude levels. The edge slicer shares the voltage comparator and amplifier of one of the data slicers. It has, therefore, effectively the same reference voltage as that data slicer. The D-FFs of the data slicers sample on the edges of a locally generated clock that are estimated to occur approximately in the middle of the symbol intervals, and the D-FF of an edge slicer samples on edges of a locally generated clock that are estimated to occur near the edge of the symbol intervals. The data slicer whose comparator and amplifier are shared with the edge slicer is typically one of the middle amplitude slicers, since statistically, more level transitions occur through a middle slicer's amplitude region and thus the edge slicer will have more opportunities for measuring the relative phases of the symbol transition edges. The output of the edge slicer, along with estimates of the data values before and after a given symbol edge, are used by the phase detector to make early or late determinations about the local sampling clock and make adjustments to its phase via a phase feedback loop within the clock recovery circuit (e.g., via a charge pump and voltage controlled oscillator).
In a 4-PAM receiver, for example, 3 data slicers and 1 edge slicer are used. The data slicers' reference voltages are set between the four modulated levels of the 4-PAM signal corresponding to the Gray encoded bit patterns {00, 01, 11, 10}. Here 00 corresponds to the lowest modulation amplitude of the 4-PAM signal, 10 corresponds to the highest modulation amplitude of the 4-PAM signal, and 01 and 11 correspond to the mid-low and mid-high modulation amplitudes, respectively. The edge slicer shares the comparator, amplifier, and reference voltage of the data slicer whose reference voltage is set between the 01 and 11 modulation levels (i.e., the mid-amplitude slicer). The data slicers slice the received 4-PAM signal roughly in the middle of the symbol interval based on an edge (e.g., the rising edge) of a locally recovered symbol period clock. The edge slicer slices the received 4-PAM signal at the estimated times of 01-11 and 00-10 transitions based on an edge (e.g., the falling edge) of that locally recovered symbol period clock. The outputs of the data slicers are processed to produce the recovered data stream, and the output of the edge slicer is used (in combination with the corresponding data slicer's output and the recovered data) in a phase detector and clock recovery circuit to adjust the phase of the recovered clock. An example phase detector used in such an application is a bang-bang phase detector as discussed in Alexander, J. D. H, “Clock Recovery From Random Binary Signals,” Electronic Letters, vol. 11, pp.541–542, October, 1975 (herein “Alexander”), incorporated herein by reference in its entirety.
Until now M-PAM (M>2) signaling has been successfully used in various data communication systems, with data rate below 2.5 Gb/s. Employing 4-PAM signaling in high speed serial communication (>2.5 Gb/s) has recently begun to emerge in order to increase the bandwidth efficiency of these systems. As an example, an 8 Gb/s serial transceiver has recently been developed using 4-PAM signaling. As the data rate increases, 4-PAM receivers begin to suffer from delay mismatch errors introduced in the three slicers, which limit the receiver's performance and reduce the timing margin. Slicer delay is defined as the time it takes a signal to propagate through the comparator, amplifier, and other circuitry of a slicer before being sampled by the slicer's D-FFs. In the design of a conventional 4-PAM receiver, each slicer exhibits a unique slicer delay. At data rates on the order of 8 Gbps, given current chip technology, the slicer delay is still small relative to the symbol period and the slicer delay differences are tolerable. At higher data rates (i.e., 10 Gb/s or higher), however, where the slicer delay differences become significant compared to the symbol interval, mismatch between slicer delays can significantly reduce the receiver's timing margin and can cause data recovery to fail in the presence of jitter on the incoming data or on the recovered clock. This is because the locally generated slicer clock (whose phase is a function of the slicer delay of the slicer to which the edge D-FF is associated) may not be aligned properly for one or more of the other data slicers (whose ideal sampling opportunities are a function of other slicer delays). Thus one or more of the data slicers may slice outside of the optimum valid data region for a symbol, (potentially with insufficient setup or hold time relative to a data transition), which may result in errors in the recovered data. Chip designers' attempts to match the slicer delays by various techniques, in addition to matching the clock buffer, clock path, and signal path delays to the slicers, have heretofore provided limited improvement in the achievable data rate of M-PAM systems.